The present application relates generally to semiconductor devices and their methods of manufacture, and more specifically to stacked fin field effect transistor (FinFET) devices and the formation of contact structures for such devices.
Fully-depleted devices such as fin field effect transistors are candidates to enable scaling of next generation gate lengths to 14 nm and below. Three-dimensional (3D) monolithic integration where transistors are stacked on top of each other is a promising approach for continued transistor density scaling. In a 3D stacked fin CMOS device, a self-aligned stack of fins can be formed where the top tier and bottom tier fins are respectively used for devices with opposite conductivity types (i.e., p-type and n-type). Such an approach enables a reduced footprint by stacking one type of transistor (e.g., a p-type FinFET) on top of a complementary type of device (e.g., an n-type FinFET), and also permits the incorporation of different channel materials for the two types of devices. In a stacked fin CMOS device, the p-type FinFET and the n-type FinFET typically share a common gate electrode.
Because of the stacked geometry, it is challenging to make electrical contact to both the top and the bottom tier fins to enable independent control thereof. In view of the foregoing, it would be advantageous to develop methods and associated structures that enable stacked FinFET architectures, which beneficially enable further device scaling.